1. Field of the Invention
This invention relates to a semiconductor device in which an output circuit for driving a large current and a control circuit for controlling this output circuit are formed on the same semiconductor substrate, and a method for manufacturing the same.
2. Background Art
Recently, with the decrease of the operating voltage of CPU (central processing unit) in computers and the like, a synchronous buck converter is often used as a CPU power supply. Furthermore, higher current response (di/dt) is increasingly required for the CPU power supply, and ripple suppression in the output voltage of the power supply is also required. Thus, enhancing the speed of the power supply has been important.
A synchronous buck converter is a step-down DC-DC converter. The DC-DC converter includes a high-side discrete element, a low-side discrete element, and a driver circuit for driving them, which are housed in separate packages and interconnected on a printed circuit board. An input potential is applied to the high-side discrete element, and a reference potential is applied to the low-side discrete element, so that these elements are alternately brought into conduction. At this time, a rectangular voltage pulse is outputted from the intermediate node between these elements and smoothed by an LC circuit to obtain a DC voltage. However, the enhancement of current response (di/dt) makes it impossible to neglect the decrease of conversion efficiency due to inductance on the printed circuit board and inductance of wire bonding in the packages.
Thus, it is contemplated to integrate the high-side element, the low-side element, and the driver circuit into one chip. However, increased chip size is needed for higher output current in this type of power supply chip, but it results in increased interconnection resistance in the chip.
In this context, a packaging method for reducing wiring resistance by bump connection is proposed in Z. J. Shen, et al., “Breaking the Scaling Barrier of Large Area Lateral Power Devices: An 1 mΩ Flip-Chip Power MOSFET with Ultra Low Gate Charge”, ISPSD '04, pp. 387-390. In this packaging method, a multilayer wiring layer is provided on the semiconductor substrate on which the elements and the driver circuit are formed, and multiple terminals of the elements and the driver circuit are bunched into fewer uppermost wirings. Bumps are provided on the uppermost wirings, and used to mount the chip on the printed circuit board. Thus, the uppermost wirings are connected to the wirings of the printed circuit board. In this case, the wiring resistance decreases with the increase of the arrangement density of bumps.
However, a problem in this technique is that the layout of the wirings of the printed circuit board constrains the bump spacing and interferes with sufficiently increasing the density. To sufficiently reduce wiring resistance, the wirings of the printed circuit board may be designed with higher density in accordance with the bump arrangement of the power supply chip. However, to this end, the method for manufacturing the printed circuit board needs to be changed so that the density of its wirings can be increased, which increases cost.